News & Events

Newsroom

JAN 23 2012 - Aldec adds Documentation for Safety-Critical Designs in ALINT™ 2012.01 JAN 19 2012 - Q1-2012 - Aldec™ Design and Verification Newsletter JAN 13 2012 - Verification Engineers are Invited to Take a Brief Survey and Receive a Chance to win an Ipad2! JAN 09 2012 - Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM™ DEC 21 2011 - Aldec 2012 Global Calendar Photo Contest Winners are Announced!

Events

JAN 27 2012 - FPGA Tokyo Conference (Trade Shows) FEB 16 2012 - 100% Signal Visibility during Emulation Dynamic Debug with HVD Technology (US) (Webinars) FEB 16 2012 - 100% Signal Visibility during Emulation Dynamic Debug with HVD Technology (Europe) (Webinars) FEB 21 2012 - International Conference on Electronic Warfare (EWCI 2012) (Trade Shows) FEB 27 2012 - Design & Verification Conference (DVCon 2012) (Trade Shows)

Recorded Webinars

Closed Loop Verification of Large Designs SystemVerilog: Who? What? When? Where? OVM and UVM - Building a SystemVerilog Testbench in Riviera-PRO Introducing Transactions in Design Verification Decrypting Encryption in HDL Design and Verification

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FPGA Design

Project Management/Integration Documentation HTML/PDF Graphical/Text Design Entry Simulation and Debugging

Functional Verification

Linting/Design Analysis UVM, OVM and VMM UVM Transaction Debugging OS-VVM™Assertions/Functional Coverage Code Coverage

Hardware Emulation Solutions

Acceleration HVD Technology Emulation Mirror-Box Technology

RTAX/RTSX Prototyping

Microsemi™ (Actel) Prototyping RTAX/RTSX Netlist Converter

DO-254 Compliance

FPGA Level In-Target Testing HDL Detailed Design and Verification Tool Assessment and Qualification Process HDL Coding Standards

Specialized Applications

Regression Manager Encryption MATLAB®/Simulink® Interface IP Generator

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