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Company Newsroom

2012
JAN 23 2012Aldec adds Documentation for Safety-Critical Designs in ALINT™ 2012.01
JAN 19 2012Q1-2012 - Aldec™ Design and Verification Newsletter
JAN 13 2012Verification Engineers are Invited to Take a Brief Survey and Receive a Chance to win an Ipad2!
JAN 09 2012Aldec and SynthWorks deliver Randomization and Functional Coverage Capabilities to VHDL Designers with OS-VVM™
2011
DEC 21 2011Aldec 2012 Global Calendar Photo Contest Winners are Announced!
NOV 15 2011Aldec Delivers HVD Technology, Providing 100% Visibility during Hardware Emulation
NOV 14 2011Aldec Delivers Complete Support for UVM 1.1, Enabling VMM and OVM Interoperability
OCT 31 2011Aldec Releases Active-HDL 9.1 Supporting Simulation of the Newest FPGA Devices
OCT 18 2011Aldec presents ‘Automated Code Reviews for Fail-Safe Designs’ at ReSpace/MAPLD 2011 Conference in Albuquerque, NM.
OCT 18 2011Aldec presents 'FPGA Level In-Hardware Verification for DO-254 Compliance' at the 30th Annual DASC in Washington
OCT 06 2011Aldec Confirms Platinum Sponsorship of 9th Annual International System-on-Chip (SoC) Conference
OCT 06 2011Q4-2011 - Aldec™ Design and Verification Newsletter
SEP 14 2011Aldec Honored for Superior FPGA Design and Verification tools
SEP 13 2011Aldec and Agnisys Partner to offer Closed Loop Verification Management to meet challenges in Verification of Modern Designs
SEP 12 2011Randall Fulton, FAA Consultant DER, to present DO-254 Training Seminar hosted by Aldec in Las Vegas, NV
AUG 03 2011Functional Verification Survey Winners
JUL 25 2011Aldec’s Emulation and Verification Tools Adopted by UC San Diego for the new Master’s Program in Wireless Embedded Systems
JUL 21 2011Q3-2011 - Aldec™ Design and Verification Newsletter
JUL 19 2011Aldec Announces 2012 Global Calendar Photo Contest!
JUL 15 2011Aldec Offers Free Assertions Seminar
JUL 11 2011Aldec Adds UVM Transaction-Level Visual Debugging
JUL 07 2011Design your own Functional Verification Tool
JUN 16 2011Aldec Demonstrates Increased Debugging Productivity at ChipEx
JUN 01 2011Aldec Announces DAC Technical Sessions to All DAC 2011 Attendees in San Diego, CA
MAY 31 2011Aldec and Avnet Asia Pacific Ink Distribution Agreement
MAY 23 2011Aldec Delivers 4 MHz Design Emulator
MAY 13 2011ALINT™ 2010.10 Service Release 1 is Now Available!
APR 28 2011PLDA and Aldec Announce PCI Express® DMA IP Supporting
APR 27 2011Q2-2011 - Aldec™ Design and Verification Newsletter
MAR 07 2011Aldec, Inc. releases Riviera-PRO 2011.02
MAR 07 2011CAST IP and Aldec Simulators Unite for Smoother FPGA and ASIC Design Flow
JAN 26 2011Aldec Adds Mirror-Box™ Debugging Technology to Hardware-assisted Simulation Platform
JAN 13 2011Q1-2011 - Aldec™ Design and Verification Newsletter
+ 2010
NOV 17 2010ALDEC Sponsors Advance Innovation Laboratory at TsingHua University and Research Center
NOV 08 2010Aldec-Israel Established, Appoints AST and Sital Technologies
OCT 19 2010Q4-2010 - Aldec™ Design and Verification Newsletter
SEP 13 2010Aldec, HighRely and Leading FPGA Vendors Establish DO-254 Ecosystem
SEP 10 2010Aldec Awarded 2010 Best FPGA Development Tool in China
SEP 01 2010VHDL IEEE 1076-2008 is Alive and Thriving
AUG 09 2010Aldec™ Announces Phase-based Linting Methodology
AUG 06 2010Q3-2010 - Aldec™ Design and Verification Newsletter
AUG 02 2010Northwest Logic Verifies Compatibility of Its IP Cores
JUN 21 2010Aldec supports OVM and UVM in Riviera-PRO
MAY 25 2010Altium adds Aldec FPGA simulation technology to Altium Designer
MAY 20 2010Q2-2010 - Aldec™ Design and Verification Newsletter
MAY 03 2010Aldec™ Opens Taiwan Branch Office
APR 19 2010Aldec™ Adds RMM Library and FPGA Primitive Support to ALINT
+ 2009
DEC 21 2009Aldec® Releases RTL Simulator with Enhanced Assertions and Xilinx® SecureIP Support
DEC 10 2009Aldec® Adds DO-254/ED-80 Library to HDL Design Rule Checker
NOV 16 2009Aldec® Announces Low-cost Linux RTL and Gate-level Simulator
NOV 04 2009Q4-2009 - Aldec® Design and Verification Newsletter
NOV 02 2009Aldec® Opens South Asia Office in Bangalore, India
OCT 14 2009EMA Partners with Aldec to Provide Cadence OrCAD Users a Complete FPGA Design Solution
JUL 23 2009Q3-2009 - Aldec® Design and Verification Newsletter
JUL 17 2009Embedded.com Crosshairs Editorial: DO-254: The other safety-critical specification, by Chris A. Ciufo (Editor)
JUL 17 2009Executive Interview: Eg3 Editor Jason McDonald interviews David Rinehart, Vice President, Aldec, Inc.
JUL 17 2009Throwing Down the Gauntlet: Aldec Makes Waves with Mixed-Language Simulation (Editor Kevin Morris, www.FPGAJournal.com)
JUL 13 2009Aldec® Delivers $1,995 Mixed Language Simulator to FPGA Market
APR 10 2009On-Line Webinar - Maximize Verification Efforts with SpringSoft’ Verdi Automated Debug and Aldec Riviera-PRO
APR 08 2009Q2-2009 - Aldec® Design and Verification Newsletter
FEB 12 2009On-Line Webinar - Aldec and SynthWorks - Implementing Constrained Random Verification with VHDL
JAN 30 2009On-Line Webinar - Aldec® and Doulos®: Migrating to Transaction-Level Modeling in SystemC
JAN 26 2009On-Site Seminar - Combining Legacy FPGA and CPLD Designs to Create a New Xilinx Virtex-5 Design
+ 2008
DEC 08 2008Aldec Releases ALINT 2008.10 supporting Mixed VHDL and Verilog Design Rule Checking
DEC 01 2008Aldec® Delivers New Dual-FPGA Prototyping Solution for Actel® RTAX4000S Space-Flight FPGA Designs
NOV 17 2008Aldec Releases Unified 64-bit Multi-Threaded HDL Design Environment
NOV 10 2008Aldec Announces OVM World Partnership and Future Support for OVM 2.0
SEP 29 2008Aldec Brings Assertions to FPGA Designers with the Release of Active-HDL 8.1
SEP 22 2008Aldec selected by Thales to deploy DO-254/ED-80 CTS for Level B Certification Compliance of Advanced Avionics System
JUL 28 2008Aldec® Announces HES 2008.07 with SCE-MI 2.0 Co-Emulation Debugging and Dynamic Debugging for ASIC Design Emulation
JUN 23 2008Aldec Delivers Clock Domain Crossing (CDC) Solution
JUN 09 2008Aldec Enhances Entire EDA Suite with Key Verification Methodologies
JUN 03 2008Aldec Releases Riviera-PRO™ 2008.06 HDL Simulator. Including New Assertions Waveform Viewer and Seamless debugging of SystemC/C++ and HDL
APR 28 2008Aldec Joins Altera DO-254 Global Partner Network Providing In-Hardware Verification of Altera’s FPGA Devices
APR 23 2008Aldec® Delivers ASIC Design Emulation
APR 21 2008Lattice and Aldec Announce New Alliance For FPGA Design And Verification
MAR 03 2008Aldec Launches Powerful Verilog Design Rule Checker
FEB 25 2008Aldec Releases Riviera-PRO™ 2008.02 with VHDL 2007, SystemC™ 2.2 and SystemVerilog (DPI)
+ 2007
DEC 20 2007Aldec releases Active-HDL 7.3 and Introduces Multi-threaded HDL Compilation
OCT 31 2007Zuken and Aldec Deliver New Design Solution: CADSTAR FPGA
OCT 11 2007Aldec Releases Riviera-PRO Targeting ASIC/FPGA Verification Market
JUN 11 2007Aldec Releases STARC Based Linting Tool
MAY 23 2007Zuken and Aldec Partner to Offer Complete FPGA Design and Verification Flow
MAY 14 2007Aldec Delivers Prototyping Solution for Actel RTAX-S Space FPGA Designs
APR 09 2007Aldec Supports The MathWorks Simulink® Fixed Point
APR 05 2007Aldec Opens Japan Office
MAR 19 2007Aldec Announces Support for Altera's Low-Cost Cyclone III FPGAs
MAR 12 2007Aldec and Actel Deliver Co-verification Solution for ARM-based FPGA Design
MAR 07 2007Aldec offers no-cost Active-HDL Student Edition. Mixed VHDL/Verilog and SystemC simulation support with direct MATLAB/Simulink™
MAR 05 2007Aldec releases 64-bit mixed HDL Simulator
MAR 05 2007Riviera-Pro™ HDL simulation environment to support POSDATA WiMAX product development
FEB 21 2007Gaisler Research and Aldec partner to increase IP core availability and portability
JAN 26 2007Aldec and nSys partner to Deliver No Cost Verification IP for Evaluation (Partnership includes support for PCI-Express, PCI-X and Arm AMBA Verification IP)
JAN 08 2007Lattice and Aldec Sign Mixed-Language Simulator Agreement
+ 2006
DEC 11 2006Aldec releases Active-HDL version 7.2 featuring new performance gains and simulation technology